react-bootstrap migration, review & parser fixes

UI / react-bootstrap:
Migrate client components to react-bootstrap (Card, Table, Form,
Alert, Badge, Nav, Button, Spinner, Row, Col): the ZXDB explorers
and detail pages (Labels, Genres, Languages, MachineTypes, Releases,
Entries), TapeIdentifier, home page, Navbar and ThemeDropdown.
Server components (home, zxdb hub, magazines, issues) keep raw
HTML+className — react-bootstrap barrel imports resolve to undefined
under Turbopack in server components. Replace bi bi-* CSS icons with
react-bootstrap-icons. Add aria-labels to search inputs and
visually-hidden captions to data tables.

Code-review remediation (docs/todo.md):
- FileViewer: replace useState-as-effect with a proper useEffect.
- register.service: restore request-level caching of parsed registers.
- middleware: convert .js to .ts, dev-only request logging.
- Extract shared types to src/types/zxdb.ts; add src/server/repo
  barrel for incremental per-domain splitting.
- Extract helpers: parseIdList (params.ts), serialize (serialize.ts),
  buildRegisterSummary/isInfoLine (register_helpers.ts).
- Add loading.tsx skeletons for dynamic ZXDB detail routes.
- generateMetadata + notFound() on entry/release/label detail pages.
- opengraph-image: stable keys; ThemeDropdown: drop hardcoded cookie
  domain; remove unused page.module.css.

Register parser & data:
- Update data/nextreg.txt from upstream tbblue (SpectrumNext FPGA):
  0x04/0x0A/0x0F/0x80/0x81 bit changes, new Issue 5 board id, 0x43
  renamed "Palette Control", 0xF0/0xF8/0xF9/0xFA now "Issues 4 and 5
  Only".
- Add reg_44 custom parser for 0x44 (Palette Value 9-bit): the two
  consecutive writes render as separate "1st write" / "2nd write"
  modes.
- Skip commented-out register headers so the disabled 0xA3 block no
  longer leaks a phantom register.
- Add detailHasContent guard so body-less registers (0xC7/0xCB/0xCF/
  0xFF) and 0xF0's leading blank no longer emit empty tab strips.
- Capture 0xF0's leading "Issues 4 and 5 Only" line as register text.
- Add isIssueRestricted (case-sensitive) to detect the issue badge
  across rewording without flagging per-bit "(issue 5 only)" notes;
  update badge label to "Issues 4 & 5 Only".

claude-opus-4-8@lucy

data/nextreg.txt

@@ -85,9 +85,9 @@ Generally a set bit indicates the property is asserted
 0x04 (04) => Config Mapping
 config mode only, bootrom disabled
 (W)
-  bit 7 = Reserved, must be 0
-  bits 6:0 = 16K SRAM bank mapped to 0x0000-0x3FFF (hard reset = 0)
-  ** Even multiplies of 256K are unreliable if storing data in sram for the next core started.
+  bits 7:0 = 16K SRAM bank mapped to 0x0000-0x3FFF (hard reset = 0)
+  ** On issue 2 pcbs, even multiplies of 256K are unreliable if storing data in sram for the next core started.
+  ** Bit 7 ignored except on issue 5 pcb
 
 0x05 (05) => Peripheral 1 Setting
 (R/W)
@@ -174,15 +174,16 @@ Joystick modes:
     01 = Multiface 128 v87.2 (enable port 0xBF, disable port 0x3F)
     10 = Multiface 128 v87.12 (enable port 0x9F, disable port 0x1F)
     11 = Multiface 1 (enable port 0x9F, disable port 0x1F)
-  bit 5 = Reserved, must be zero
+  bit 5 = 1 to swap sd0 and sd1 (hard reset = 0) (config mode only) *
   bit 4 = Enable divmmc automap (hard reset = 0)
   bit 3 = 1 to reverse left and right mouse buttons (hard reset = 0)
-  bit 2 = Reserved, must be zero
+  bit 2 = Reserved, must be 0
   bits 1:0 = mouse dpi (hard reset = 01)
     00 = low dpi
     01 = default
     10 = medium dpi
     11 = high dpi
+  * only affects future writes to port 0xE7
 
 0x0B (11) => Joystick I/O Mode
 (R/W) (soft reset = 0x01)
@@ -219,6 +220,7 @@ Sub-minor number
     0000 = ZXN Issue 2, XC6SLX16-2FTG256, 128Mbit W25Q128JV, 24bit spi, 64K*8 core size
     0001 = ZXN Issue 3, XC6SLX16-2FTG256, 128Mbit W25Q128JV, 24bit spi, 64K*8 core size
     0010 = ZXN Issue 4, XC7A15T-1CSG324, 256Mbit MX25L25645G, 32bit spi, 64K*34 core size
+    0011 = ZXN Issue 5, XC7A35T-2CSG324, 256Mbit MX25L25645G, 32bit spi, 64K*34 core size
 
 0x10 (16) => Core Boot
 (R)
@@ -525,7 +527,7 @@ Writable in config mode only.
     the mask with the attribute byte and the PAPER and border colour are again both taken
     from the fallback colour in nextreg 0x4A.
 
-0x43 (67) => ULA Palette Control
+0x43 (67) => Palette Control
 (R/W)
   bit 7 = Disable palette write auto-increment (soft reset = 0)
   bits 6-4 = Select palette for reading or writing (soft reset = 000)
@@ -787,6 +789,7 @@ Writable in config mode only.
   bit 6 = 1 to allow peripherals to override the ULA on some even port reads (rotronics wafadrive)
   bit 5 = 1 to disable expansion bus nmi debounce (opus discovery)
   bit 4 = 1 to propagate the max cpu clock at all times including when the expansion bus is off
+  bit 3 = 1 to enable +3 fdc signals on expansion bus (issue 5 only)
   bits 1-0 = max cpu speed when the expansion bus is on (currently fixed at 00 = 3.5MHz)
 
 0x85,0x84,0x83,0x82 (133-130) => Internal Port Decoding Enables (0x85 is MSB) (soft reset if bit 31 = 1, hard reset if bit 31 = 0 : all 1)
@@ -824,6 +827,7 @@ Writable in config mode only.
   bit 26 = port eff7 pentagon 1024 memory
   bit 27 = port 183b,193b,1a3b,1b3b,1c3b,1d3b,1e3b,1f3b z80 ctc
   ...
+  ...
   bit 31 = register reset mode (soft or hard reset selection)
   -----
   The internal port decoding enables always apply.
@@ -1202,7 +1206,7 @@ progress is made in the main program.
 --
 
 0xF0 (240) => XDEV CMD
-R/W Issue 4 Only - (soft reset = 0x80)
+R/W Issues 4 and 5 Only - (soft reset = 0x80)
   Select Mode
     (R)
       bit 7 = 1 if in select mode
@@ -1238,7 +1242,7 @@ R/W Issue 4 Only - (soft reset = 0x80)
   *** Exit select mode by writing zero to bit 7; thereafter the particular device is attached to the nextreg
 
 0xF8 (248) => XADC REG
-(R/W Issue 4 Only) (hard reset = 0)
+(R/W Issues 4 and 5 Only) (hard reset = 0)
   bit 7 = 1 to write to XADC DRP port, 0 to read from XADC DRP port **
   bits 6:0 = XADC DRP register address DADDR
   * An XADC register read or write is/ initiated by writing to this register
@@ -1246,12 +1250,12 @@ R/W Issue 4 Only - (soft reset = 0x80)
   ** Reads as 0
 
 0xF9 (249) => XADC D0
-(R/W Issue 4 Only) (hard reset = 0)
+(R/W Issues 4 and 5 Only) (hard reset = 0)
   bits 7:0 = LSB data connected to XADC DRP data bus D7:0
   * DRP reads store result here, DRP writes take value from here
 
 0xFA (250) => XADC D1
-(R/W Issue 4 Only) (hard reset = 0)
+(R/W Issues 4 and 5 Only) (hard reset = 0)
   bits 7:0 = MSB data connected to XADC DRP data bus D15:8
   * DRP reads store result here, DRP writes take value from here